Bay Area Chip Design was formed to tackle today's high NRE costs and low volume requirements of cell-based designs by use of new technology to capture the simplicity and short design cycle times of traditional ASICs with the benefits of faster timing closure, higher performance, and significantly lower NRE cost.

More and more, today’s designers of high-complexity ICs are severely challenging the limits of the prevalent cell-based technology in terms of NRE and cost with today's latest technologies. The once short, predictable design cycles long associated with this traditional approach are now but a thing of the past.

To gain a competitive edge and improve profits, IC companies need to move their products quickly to market while controlling costs. With deep submicron processes, cell-based flows have come up against major timing closure bottlenecks that stretch design cycles indefinitely.

Bay Area Chip Design’s technology was specifically developed to handle deep submicron complexity and obliterate the NRE, cost, and time-to-market bottleneck that plagues traditional cell-based techniques.

Bay Area Chip Design was formed to present complex device designers with an automated and flexible design environment to address the deep sub-micron rapid integration and timing closure issues that have severely challenged the prevalent cell-based IC implementation technology.