Mid-Volume ASIC design dilemma

Standard Cell ASICs have served our industry well through many process migrations. Now, Moore's law is outstripping the ability to utilize available silicon with an appropriate level of cost and risk. With mask costs passing $1M, design cycles expanding past a year and reliability questions arising from very Deep Sub-Micron physical effects, it now requires a large annual production run to justify a custom device. But, what if you still need the performance of a custom ASIC?

Roughly 1/3 of ASIC designs need lower part cost than FPGA (10k-100K volume), but NRE charges, time to market, and total design cost is too high to use cell-based ASIC.

Source: Gartner/Dataquest

The battle for middle ground is best filled by Structured ASICs. Structured ASICs offer a cost-effective solution for the mid-volume market with 75% less development costs than cell-based ASICs and unit costs up-to 90% less than complex FPGAs.

What is Structured ASIC?

Structured ASIC have fewer layers to customize which implies much shorter fabrication time. Structured ASICs have fixed layers to incorporate I/Os, RAMs, Power lines, PLLs, and other IP. Structured ASICs are not Gate Arrays. Gate arrays address the manufacturing cycle time issue with custom ASICs. But, Structured ASICs address the design implementation issues with custom ASICS such as NRE charges, time to handoff, cost of design tools and engineering resources, number of design functions to be performed, IP integration, and unpredictable layout turnaround times of custom ASICs.

Structured ASIC dramatically shortens the design cycle by simpler design flow which cuts down engineering time by months and reducing fabrication time to weeks compared to months for cell-based ASICs.